1. Field of the Invention
The present invention relates to a method for compressing a semiconductor integrated circuit. This invention relates to, for example, a semiconductor integrated circuit that is designed by arranging standard cells.
2. Description of the Related Art
In recent years, remarkable developments have been made in integration density of a semiconductor integrated circuit (LSI: Large Scale Integrated Circuit). Along with these developments, a load on LSI designers has become increasingly heavier.
Conventionally, an entire LSI chip is designed as a whole. However, with an increase in the scale of an LSI, it is expected that the optimization of LSI design would become considerably difficult in the near future. An optimizing process is carried out by a design tool, but the time needed for the process has increased to several days or a week. In worst cases, the optimization is failed or is not completed.
Under the circumstances, a method of designing one chip by dividing the chip into a plurality of regions has been proposed. This proposal is disclosed in, e.g. AmmoCore Technology, fabrix Preliminary Datasheet, <URL: http://www.ammocore.com/ammocore_fabrix.pdf>, <URL: http://www.ammocore.com/fabrix_overview.pdf>. In this proposal, each of the divided regions is individually subjected to an optimizing process, following which the respective regions are connected. According to the proposal, the optimizing process can be performed in a parallel fashion, and the time needed for the process can be reduced to several hours to one day.
In the above prior-art proposal, however, it is difficult to efficiently use all regions, and a variance occurs in density of each region (high-density region/low-density region). Consequently, the efficiency of use of the area of the chip lowers, thus it is difficult to increase the compression ratio in LSI design.